A press release was issued regarding the research results of Professor Ken Takeuchi (Faculty of Science and Engineering; Department of Electrical, Electronic, and Communication Engineering).

Professor Takeuchi has succeeded in reducing by 85% the errors associated with the reading of high-capacity, low-cost TLC (Triple Level Cell) flash memory, as well as in increasing the number of time that reading can be performed by 6.7 times. In this research, the reduction of errors associated with the reading and increase in number of possible readings was enabled by having memory automatically distinguish data characteristics (access frequency, etc.), store data in different memory regions based on data characteristics, and applying the optimal read-out voltage.

Currently, TLC flash memory is mainly used in devices such as smartphones and tablets. Further development of this technology will enable stable reading, thus realizing an even higher level of reliability and speed for memory. As a result, there are expectations for usage of flash memory in its next major market of a storage medium for cloud data centers.

This research was made possible by the JST Strategic Basic Research Programs CREST as part of the “Highly-Reliable Memory Systems for Realization of Long-Term Storage of Digital Data” research theme in the “Innovative Nano-electronics through Interdisciplinary Collaboration among Material, Device and System Layers” research field.

The research results discussed in this press release were announced at the IEEE Symposium on VLSI Technology which was held in Honolulu from June 13 to 16, 2016.

Please visit the links listed below for further information.

• Details of press release (PDF 561 kb)
• Green-Nano LSI Circuit System / Takeuchi Laboratory
• Chuo Online “Engineers Can’t Afford to Ignore the Business World”
• IEEE Symposium on VLSI Technology and Circuits